In a digital phase locked loop (DPLL) architecture for local oscillator (LO) generation, the voltage controlled oscillator (VCO) phase is typically measured and compared to a high purity low-frequency reference signal using a time-to-digital converter (TDC). The error phase between the VCO and reference signals is filtered and used to set the VCO frequency. In typical implementations of a TDC, a mismatch occurs between buffer cells of the TDC. This mismatch may produce a non-uniform quantization characteristic. As a result, the VCO phase, as measured by the TDC, shows an error that inherits the same periodicity as that of the VCO phase, which in turn is set by the desired ratio between output frequency and reference signal frequency. This periodic error appears in the DPLL output signal spectrum as spurious sidebands around a carrier. Such spurs limit the ability to use a DPLL employing a conventional TDC architecture for frequency generation where high spectral purity is desired.
In addition, the resolution of a TDC is typically not known precisely because the resolution may be process-, voltage-, and temperature dependent. Without knowledge of TDC resolution, the TDC cannot output a number that exactly represents the phase difference between its two inputs, but rather a scaled phase difference between the inputs. The phase wrapping effect in a TDC device serves to periodically reset this incorrect phase difference such that the periodicity appears at the DPLL output signal spectrum as spurious sidebands around the carrier. These spurs further limit the application of a DPLL as a frequency generator where high spectral purity is required, because filtering of such spurs would require a low bandwidth DPLL. It is with respect to these and other considerations that the present improvements have been needed.